1. Field of the Invention
The method of predicting quiescent current variation of an integrated circuit die from a derating factor of a process monitor disclosed herein is directed to testing and screening of integrated circuit die. More specifically, but without limitation thereto, this method is directed to detecting defective die by comparing the measured quiescent current of a die to a selected range of quiescent current values predicted for a defect free die.
2. Description of Related Art
Quiescent current testing has proven to be an effective approach to screening defects during manufacturing and testing of semiconductor devices. As semiconductor technology progresses toward reduced transistor size, single limit quiescent current (IDDQ) testing becomes less effective due to large variances in quiescent current resulting from process shifts during manufacturing. The large variances in quiescent current are likely to result in screening good die as defective or in passing defective die.